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74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
Rev. 05 -- 25 August 2009 Product data sheet
1. General description
The 74LVC245A; 74LVCH245A are 8-bit transceivers featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features an output enable (OE) input for easy cascading and a send/receive (DIR) input for direction control. OE controls the outputs so that the buses are effectively isolated. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. The 74LVCH245A bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.
2. Features
I I I I I I I I I 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Inputs accept voltages up to 5.5 V High-impedance when VCC = 0 V Bushold on all data inputs (74LVCH245A only) Complies with JEDEC standard no. 8-1A ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from -40 C to +85 C and -40 C to +125 C
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
3. Ordering information
Table 1. Ordering information Package Temperature range Name 74LVC245AD 74LVCH245AD 74LVC245ADB 74LVCH245ADB 74LVC245APW 74LVCH245APW 74LVC245ABQ 74LVCH245ABQ 74LVC245ABX 74LVCH245ABX -40 C to +125 C DHXQFN20U -40 C to +125 C DHVQFN20 -40 C to +125 C TSSOP20 -40 C to +125 C SSOP20 -40 C to +125 C SO20 Description plastic small outline package; 20 leads; body width 7.5 mm plastic shrink small outline package; 20 leads; body width 5.3 mm Version SOT163-1 SOT339-1 Type number
plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm SOT764-1 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm plastic dual in-line compatible thermal enhanced extremely thin quad flat package; no leads; 20 terminals; UTLP based; body 2.5 x 4.5 x 0.5 mm SOT1045-1
4. Functional diagram
1
DIR OE
19
2
A0 B0 18
3
A1 B1 17 19 B2 16 1 G3 3EN1 3EN2
4
A2
5
A3 B3 15 2 B4 14 3 4 B5 13 5 6 B6 12 7 8 B7 11 9
1 2 18 17 16 15 14 13 12 11
mna175
6
A4
7
A5
8
A6
9
A7
mna174
Fig 1.
Logic diagram
Fig 2.
IEC logic symbol
(c) NXP B.V. 2009. All rights reserved.
74LVC_LVCH245A_5
Product data sheet
Rev. 05 -- 25 August 2009
2 of 17
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
5. Pinning information
5.1 Pinning
74LVC245A 74LVCH245A
terminal 1 index area 20 VCC 19 OE 18 B0 17 B1 16 B2 15 B3 14 B4 GND(1) GND 10 B7 11 13 B5 12 B6 DIR 2 3 4 5 6 7 8 9 1 A0 A1 DIR A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 20 VCC 19 OE 18 B0 17 B1 16 B2 15 B3 14 B4 13 B5 12 B6 11 B7
001aak292
74LVC245A 74LVCH245A
A2 A3 A4 A5 A6 A7
GND 10
001aak293
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 3.
Pin configuration for SO20 and (T)SSOP20
Fig 4.
Pin configuration for DHVQFN20 and DHXQFN20U
5.2 Pin description
Table 2. Symbol DIR A0 to A7 GND B0 to B7 OE VCC Pin description Pin 1 2, 3, 4, 5, 6, 7, 8, 9 10 18, 17, 16, 15, 14, 13, 12, 11 19 20 Description direction control data input/output ground (0 V) data input/output output enable input (active LOW) supply voltage
74LVC_LVCH245A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 25 August 2009
3 of 17
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
6. Functional description
Table 3. Inputs OE L L H
[1]
Function selection[1] Inputs/outputs DIR L H X An An = Bn inputs Z Bn inputs Bn = An Z
H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high impedance OFF-state.
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot
[1] [2] [3]
Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation
Conditions VI < 0 V
[1]
Min -0.5 -50 -0.5 [2] [2]
Max +6.5 +6.5 50 VCC + 0.5 +6.5 50 100 +150 500
Unit V mA V mA V V mA mA mA C mW
VO > VCC or VO < 0 V output HIGH or LOW output 3-state VO = 0 V to VCC
-0.5 -0.5 -100 -65
Tamb = -40 C to +125 C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed. The output voltage ratings may be exceeded if the output current ratings are observed. For SO20 packages: above 70 C derate linearly with 8 mW/K. For (T)SSOP20 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN20 and DHXQFN20U packages: above 60 C derate linearly with 4.5 mW/K.
74LVC_LVCH245A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 25 August 2009
4 of 17
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
8. Recommended operating conditions
Table 5. Symbol VCC Recommended operating conditions Parameter supply voltage Conditions maximum speed performance functional VI VO Tamb t/V input voltage output voltage ambient temperature input transition rise and fall rate output HIGH or LOW output 3-state in free air VCC = 1.2 V to 2.7 V VCC = 2.7 V to 3.6 V Min 2.7 1.2 0 0 0 -40 0 0 Typ Max 3.6 3.6 5.5 VCC 5.5 +125 20 10 Unit V V V V V C ns/V ns/V
9. Static characteristics
Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol VIH VIL VOH Parameter HIGH-level input voltage LOW-level input voltage Conditions VCC = 1.2 V VCC = 2.7 V to 3.6 V VCC = 1.2 V VCC = 2.7 V to 3.6 V -40 C to +85 C Min VCC 2.0 VCC - 0.2 2.2 2.4 2.2 [2]
-40 C to +125 C Unit Min VCC 2.0 VCC - 0.3 2.05 2.25 2.0 Max 0 0.8 0.3 0.6 0.8 20 20 V V V V V V V V V V V A A 0
Typ[1] VCC 0 0.1 0.1
Max
0.8 0.20 0.40 0.55 5 5
HIGH-level output VI = VIH or VIL voltage IO = -100 A; VCC = 2.7 V to 3.6 V IO = -12 mA; VCC = 2.7 V IO = -18 mA; VCC = 3.0 V IO = -24 mA; VCC = 3.0 V
VOL
LOW-level output voltage
VI = VIH or VIL IO = 100 A; VCC = 2.7 V to 3.6 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V
II IOZ
input leakage current OFF-state output current
VI = 5.5 V or GND; VCC = 3.6 V VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V
-
[2][3]
IOFF ICC ICC
power-off leakage VI or VO = 5.5 V; VCC = 0.0 V current supply current additional supply current VI = VCC or GND; IO = 0 A; VCC = 3.6 V per input pin; VI = VCC - 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V
-
0.1 0.1 5
10 10 500
-
20 40 5000
A A A
74LVC_LVCH245A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 25 August 2009
5 of 17
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
Table 6. Static characteristics ...continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol CI CI/O IBHL IBHH IBHLO IBHHO Parameter input capacitance input/output capacitance bus hold LOW current bus hold HIGH current bus hold LOW overdrive current bus hold HIGH overdrive current VCC = 3.0 V; VI = 0.8 V VCC = 3.0 V; VI = 2.0 V VCC = 3.6 V VCC = 3.6 V
[4][5]
Conditions
-40 C to +85 C Min 75 -75 500 -500 Typ[1] 4.0 10 Max -
-40 C to +125 C Unit Min 60 -60 500 -500 Max pF pF A A A A
[4][5]
[4][6]
[4][6]
[1] [2] [3] [4] [5] [6]
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal. For I/O ports the parameter IOZ includes the input leakage current. Valid for data inputs of bus hold parts only (74LVCH245A). Note that control inputs do not have a bus hold circuit. The specified sustaining current at the data input holds the input below the specified VI level. The specified overdrive current at the data input forces the data input to the opposite input state.
10. Dynamic characteristics
Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter tpd propagation delay Conditions An to Bn; see Figure 5 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V ten enable time OE to An or Bn; see Figure 6 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tdis disable time OE to An or Bn; see Figure 6 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tsk(o) output skew time
[3] [4] [3] [1] [3] [1] [1]
-40 C to +85 C Min 1.5 1.5 1.5 1.5 1.5 1.7 Typ[2] 17.0 3.4 2.9 22.0 5.0 4.0 12.0 3.6 3.4 Max 7.3 6.3 9.5 8.5 8.0 7.0 1.0
-40 C to +125 C Unit Min 1.5 1.5 1.5 1.5 1.5 1.7 Max 9.5 8.0 12.0 11.0 10.0 9.0 1.5 ns ns ns ns ns ns ns ns ns ns
74LVC_LVCH245A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 25 August 2009
6 of 17
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
Table 7. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter CPD power dissipation capacitance Conditions per buffer; VI = GND to VCC; VCC = 3.3 V
[5]
-40 C to +85 C Min Typ[2] 15 Max -
-40 C to +125 C Unit Min Max pF
[1]
tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. Typical values are measured at Tamb = 25 C. Typical values are measured at Tamb = 25 C and VCC = 3.3 V. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL x VCC2 x fo) = sum of the outputs.
[2] [3] [4] [5]
11. AC waveforms
VI An, Bn input GND tPLH VOH Bn, An output VOL VM VM
mna176
VM
VM
tPHL
See Table 8 for measurement points VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5.
Input (An, Bn) to output (Bn, An) propagation delays and output transition times
74LVC_LVCH245A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 25 August 2009
7 of 17
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
VI OE input GND t PLZ VCC output LOW-to-OFF OFF-to-LOW VOL t PHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled
mna367
VM
t PZL
VM VX t PZH VY VM
See Table 8 for measurement points VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Table 8. VCC 1.2 V 2.7 V
Enable and disable times Measurement points Input VI VCC 2.7 V 2.7 V VM 0.5 x VCC 1.5 V 1.5 V Output VM 0.5 x VCC 1.5 V 1.5 V VX VOL + 0.1 V VOL + 0.3 V VOL + 0.3 V VY VOH - 0.1 V VOH - 0.3 V VOH - 0.3 V
Supply voltage
3.0 V to 3.6 V
74LVC_LVCH245A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 25 August 2009
8 of 17
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
VI negative pulse 0V
tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW
VEXT VCC VI VO
RL
VM
VI positive pulse 0V
VM
G
RT
DUT
CL RL
001aae331
Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times.
Fig 7. Table 9.
Test circuit for measuring switching times Test data Input VI tr, tf 2.5 ns 2.5 ns 2.5 ns VCC 2.7 V 2.7 V Load CL 50 pF 50 pF 50 pF RL 500 [1] 500 500 VEXT tPLH, tPHL open open open tPLZ, tPZL 2 x VCC 2 x VCC 2 x VCC tPHZ, tPZH GND GND GND
Supply voltage 1.2 V 2.7 V 3.0 V to 3.6 V
[1]
The circuit performs better when RL = 1 k.
74LVC_LVCH245A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 25 August 2009
9 of 17
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.016 0.394
0.035 0.004 0.016
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 8.
Package outline SOT163-1 (SO20)
(c) NXP B.V. 2009. All rights reserved.
74LVC_LVCH245A_5
Product data sheet
Rev. 05 -- 25 August 2009
10 of 17
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 10 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 7.4 7.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.9 0.5 8 o 0
o
Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 9.
Package outline SOT339-1 (SSOP20)
(c) NXP B.V. 2009. All rights reserved.
74LVC_LVCH245A_5
Product data sheet
Rev. 05 -- 25 August 2009
11 of 17
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c y HE vMA
Z
20
11
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
10
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8 o 0
o
Fig 10. Package outline SOT360-1 (TSSOP20)
74LVC_LVCH245A_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 25 August 2009
12 of 17
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm
D
B
A
A A1 E c
terminal 1 index area
detail X
terminal 1 index area e 2 L
e1 b 9 vMCAB wM C y1 C
C y
1 Eh 20
10 e 11
19 Dh 0
12 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.6 4.4 Dh 3.15 2.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT764-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
Fig 11. Package outline SOT764-1 (DHVQFN20)
74LVC_LVCH245A_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 25 August 2009
13 of 17
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
DHXQFN20U: plastic dual in-line compatible thermal enhanced extremely thin quad flat package; no leads; 20 terminals; UTLP based; body 2.5 x 4.5 x 0.5 mm
SOT1045-1
D
B
A
E
A
A1
detail X terminal 1 index area
terminal 1 index area L1
2
e1 e b
9
v w
M M
CAB C
C y1 C y
L
1
10
Eh
20 11
e
19
12
Dh
X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.30 0.18 D 4.6 4.4 Dh 3.35 3.05 E 2.6 2.4 Eh 1.35 1.05 e 0.5 e1 3.5 L 0.45 0.25 L1 0.13 0.05 v 0.1 w 0.05 y 0.05 y1 0.1
OUTLINE VERSION SOT1045-1
REFERENCES IEC --JEDEC JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 07-12-01 09-08-04
Fig 12. Package outline SOT1045-1 (DHXQFN20U)
74LVC_LVCH245A_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 25 August 2009
14 of 17
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
13. Abbreviations
Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic
14. Revision history
Table 11. Revision history Release date Data sheet status 20090825 Product data sheet Product data sheet Change notice Supersedes 74LVC_LVCH245A_4 74LVC_LVCH245A_3 Document ID 74LVC_LVCH245A_5 Modifications: 74LVC_LVCH245A_4 Modifications:
* * * *
New SOT1045-1 package outline drawing (DHXQFN20U package). The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74LVC245ABX and 74LVCH245ABX (DHXQFN20U package) Product specification Product specification Product specification 74LVC245A_74LVCH245A_2 74LVC245A_74LVCH245A_1 -
20090703
74LVC_LVCH245A_3
20030507
74LVC245A_74LVCH245A_2 20020620 74LVC245A_74LVCH245A_1 19971219
74LVC_LVCH245A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 25 August 2009
15 of 17
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC_LVCH245A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 25 August 2009
16 of 17
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
17. Contents
1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 August 2009 Document identifier: 74LVC_LVCH245A_5

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